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LAN8804 Fiches technique(PDF) 13 Page - Microchip Technology

No de pièce LAN8804
Description  4-Port Gigabit Ethernet Transceiver with QSGMII Support
PDF  91 Pages
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Fabricant  MICROCHIP [Microchip Technology]
Site Internet  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN8804 Fiches technique(HTML) 13 Page - Microchip Technology

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LAN8804
© 2024 Microchip Technology Inc. and its subsidiaries
DS00003591G-page 13
3.2
Pin Descriptions
This section contains descriptions of the various LAN8804 pins. The “
_N” symbol in the signal name indicates that the
active, or asserted, state occurs when the signal is at a low voltage level. For example,
RESET_N indicates that the
reset signal is active low. When “
_N” is not present after the signal name, the signal is asserted when at the high voltage
level. The pin buffer type definitions are detailed in Section 1.2, "Buffer Types".
The pin function descriptions have been broken into functional groups as follows:
• Ethernet Media Interface Pins
• QSGMII Interface Pins
• System Clock Pins
• Miscellaneous Pins
• JTAG Pins
• Configuration Strap Input Pins
• Power and Ground Pins
TABLE 3-2:
ETHERNET MEDIA INTERFACE PINS
Name
Symbol
Buffer
Type
Description
Ethernet Port 0
TX/RX Positive
Channel A
TX_RXP_A_0
AIO
Port 0 Channel A positive signal of differential pair
Ethernet Port 0
TX/RX Negative
Channel A
TX_RXN_A_0
AIO
Port 0 Channel A negative signal of differential pair
Ethernet Port 0
TX/RX Positive
Channel B
TX_RXP_B_0
AIO
Port 0 Channel B positive signal of differential pair
Ethernet Port 0
TX/RX Negative
Channel B
TX_RXN_B_0
AIO
Port 0 Channel B negative signal of differential pair
Ethernet Port 0
TX/RX Positive
Channel C
TX_RXP_C_0
AIO
Port 0 Channel C positive signal of differential pair
Ethernet Port 0
TX/RX Negative
Channel C
TX_RXN_C_0
AIO
Port 0 Channel C negative signal of differential pair
Ethernet Port 0
TX/RX Positive
Channel D
TX_RXP_D_0
AIO
Port 0 Channel D positive signal of differential pair
Ethernet Port 0
TX/RX Negative
Channel D
TX_RXN_D_0
AIO
Port 0 Channel D negative signal of differential pair
Ethernet Port 1
TX/RX Positive
Channel A
TX_RXP_A_1
AIO
Port 1 Channel A positive signal of differential pair
Ethernet Port 1
TX/RX Negative
Channel A
TX_RXN_A_1
AIO
Port 1 Channel A negative signal of differential pair
Ethernet Port 1
TX/RX Positive
Channel B
TX_RXP_B_1
AIO
Port 1 Channel B positive signal of differential pair
Ethernet Port 1
TX/RX Negative
Channel B
TX_RXN_B_1
AIO
Port 1 Channel B negative signal of differential pair



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