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AMD-K6-2E/233AMZ Fiches technique(PDF) 64 Page - Advanced Micro Devices |
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AMD-K6-2E/233AMZ Fiches technique(HTML) 64 Page - Advanced Micro Devices |
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64 / 332 page ![]() 46 Software Environment Chapter 3 AMD-K6™-2E Processor Data Sheet 22529B/0—January 2000 Preliminary Information Page Flush/Invalidate Register (PFIR) The AMD-K6-2E processor contains the Page Flush/Invalidate Register (PFIR) (see Figure 39) that allows cache invalidation and optional flushing of a specific 4-Kbyte page from the linear address space. Using this register can result in a much lower cycle count for flushing particular pages versus flushing the entire cache. When the PFIR is written to (using the WRMSR instruction), the invalidation and, optionally, the flushing begins. Figure 39. Page Flush/Invalidate Register (PFIR) LINPAGE 10 63 F / I Symbol Description Bit LINPAGE 20-bit Linear Page Address 31-12 PF Page Fault Occurred 8 F/I Flush/Invalidate Command 0 11 31 12 32 P F 98 7 Reserved |
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