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ADS6445 Fiches technique(PDF) 66 Page - STMicroelectronics |
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ADS6445 Fiches technique(HTML) 66 Page - STMicroelectronics |
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66 / 75 page ![]() www.ti.com ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 Table 30. Timings for 2-Wire Interface, SDR Bit Clock DATA SETUP TIME, tsu DATA HOLD TIME, th tdelay SAMPLING ns ns ns SERIALIZATION FREQUENCY MSPS MIN TYP MAX MIN TYP MAX MIN TYP MAX 65 0.8 1 1 1.2 Fs ≥ 40 MSPS 40 1.5 1.7 1.6 1.8 3.4 4.4 5.4 14 × 20 3.4 3.6 3.3 3.5 Fs < 40 MSPS 10 6.9 7.2 6.6 6.9 3.7 5.2 6.7 65 0.65 0.85 0.8 1.0 Fs ≥ 40 MSPS 40 1.3 1.5 1.4 1.6 3.4 4.4 5.4 16 × 20 2.8 3.0 2.8 3.0 Fs < 40 MSPS 10 6.0 6.3 5.8 6.1 3.7 5.2 6.7 Table 31. Output Jitter (applies to all interface options) BIT CLOCK JITTER, CYCLE-CYCLE FRAME CLOCK JITTER, CYCLE-CYCLE SAMPLING FREQUENCY ps, peak-peak ps, peak-peak MSPS MIN TYP MAX MIN TYP MAX ≥ 65 350 75 66 Submit Documentation Feedback |
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