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ADS6445 Fiches technique(PDF) 59 Page - STMicroelectronics |
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ADS6445 Fiches technique(HTML) 59 Page - STMicroelectronics |
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59 / 75 page ![]() www.ti.com 2-WIRE INTERFACE - 14 × SERIALIZATION ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 The 14-bit ADC data is serialized and output over two LVDS pairs. A frame clock at 1 × sample frequency is also available with an SDR bit clock. With DDR bit clock option, the frame clock frequency is 0.5 × sample frequency. The output data rate will be 7 × sample frequency as 7 data bits are output every clock cycle on each wire. Each ADC sample is sent over the 2 wires as byte-wise or bit-wise or word-wise. 59 Submit Documentation Feedback |
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