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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AVR32AP Fiches technique(PDF) 5 Page - ATMEL Corporation |
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AVR32AP Fiches technique(HTML) 5 Page - ATMEL Corporation |
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5 / 181 page  5 32001A–AVR32–06/06 AVR32 1.6 The AVR32 AP implementation The first implementation of the AVR32B microarchitecture is designed as an application proces- sor and called AVR32 AP. This implementation targets high-performance applications in the DSP, multimedia and wireless segment, and provides: • Advanced OCD system. • Efficient data and instruction caches. • Full MMU. • Java acceleration is implemented in hardware. • Fast interrupt handling is provided through shadowed register banks for interrupt priority 3. • SIMD extension. • DSP extension. • Service Access Port (SAP) that gives an external JTAG controller access to memories and registers inside the AVR32 AP core. Figure 1-1 on page 5 displays the contents of AVR32 AP: Figure 1-1. Overview of AVR32 AP. AVR32 AP CPU pipeline with Java accelerator Dcache controller High Speed bus master Icache controller High Speed bus master MMU Cache RAM interface Cache RAM interface BTB RAM interface Tightly Coupled Bus OCD system Reset control Service Access Port |
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