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AVR32AP Fiches technique(PDF) 39 Page - ATMEL Corporation

No de pièce AVR32AP
Description  32-bit AVR Microcontroller
PDF  181 Pages
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Fabricant  ATMEL [ATMEL Corporation]
Site Internet  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AVR32AP Fiches technique(HTML) 39 Page - ATMEL Corporation

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39
32001A–AVR32–06/06
AVR32
Since the INT0 exception is unrelated to the instruction stream, the instructions in the pipeline
are allowed to complete. After finishing the INT0 exception routine, execution should continue at
the instruction following the last completed instruction in the instruction stream.
RSR_INT0 = SR;
RAR_INT0 = Address of first noncompleted instruction;
SR[R] = 0;
SR[J] = 0;
SR[M2:M0] = B’010;
SR[I0M] = 1;
PC = EVBA | INTERRUPT_VECTOR_OFFSET;
3.11.1.12
Instruction Address Exception
The Instruction Address Error exception is generated if the generated instruction memory
address has an illegal alignment.
RSR_EX = SR;
RAR_EX = PC;
TLBEAR = FAILING_VIRTUAL_ADDRESS;
TLBEHI[VPN] = FAILING_PAGE_NUMBER;
SR[R] = 0;
SR[J] = 0;
SR[M2:M0] = B’110;
SR[EM] = 1;
SR[GM] = 1;
PC = EVBA | 0x14;
3.11.1.13
ITLB Miss Exception
The ITLB Miss exception is generated when no TLB entry matches the instruction memory
address, or if the Valid bit in a matching entry is 0.
RSR_EX = SR;
RAR_EX = PC;
TLBEAR = FAILING_VIRTUAL_ADDRESS;
TLBEHI[VPN] = FAILING_PAGE_NUMBER;
TLBEHI[I] = 1;
SR[R] = 0;
SR[J] = 0;
SR[M2:M0] = B’110;
SR[EM] = 1;
SR[GM] = 1;
PC = EVBA | 0x50;



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