| Moteur de recherche de fiches techniques de composants électroniques |
|
PCD5042H Fiches technique(PDF) 20 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
PCD5042H Fiches technique(HTML) 20 Page - NXP Semiconductors |
|
20 / 28 page ![]() 1996 Oct 31 20 Philips Semiconductors Objective specification DECT burst mode controller PCD5042 Notes to the characteristics 1. VDD = 3.0 V; fclk =13.824 MHz; no external load; one speech link active (under typical conditions). 2. VDD = 3.0 V; fclk =13.824 MHz; no external load; after reset. 3. Maximum differential non-linearity at supply voltage 5.5 V and VREF =1V. 4. Supply current IDD(stb)(comp) flows when COMP_NE is HIGH. Supply current IDD(idle)(comp) flows when the comparator is in active mode (COMP_NE is LOW). It is the DC current of the comparator when it is not switching, and V(COMP_INP) < V(COMP_INM). The active mode supply current IDD(1MHz) includes the output pulse rate of 1 MHz. 5. For input pins COMP_INP, COMP_INM, COMP_NE. 6. For input pin COMP_NE. 7. The minimum input common mode voltage will be measured at DC levels with, COMP_INM at 1 V DC ±30 mV. The same goes for the maximum input common mode voltage at (VDD − 0.5V). 8. These values are not tested in production, and are based upon theoretical estimates and laboratory tests. 9. The propagation delay tpd is measured from the time the differential input voltage equals the offset voltage, to the 50% point of the output transition. The initial differential input voltage is 100 mV and the propagation delay is specified for an input overdrive of 30 mV, and a load capacitance of 50 pF. tpd is valid for both the positive and negative going output transition. The maximum value is valid for the total ranges of temperature, supply voltage and common mode input voltage. The worst case operation conditions are at the minimum supply voltage, the lowest operating temperature and the minimum input common mode voltage. The delay difference ∆tpd gives the difference between tpd for the rising output transition and tpd for the falling output transition and is valid for all operating conditions. The test method to check the maximum delay difference is by measuring the RMS voltage of the output signal. |
|
Lien URL |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Lien vers la fiche technique | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |