PCD5042H datasheet(14/28 Pages) PHILIPS

14 / 28 page

1996 Oct 31

Philips Semiconductors

Objective speciﬁcation

DECT burst mode controller

PCD5042

6.5.7

LOCAL CALL SWITCHING (see Fig.9)

The PCD5042 provides a local call switching function in

the base station. It will store incoming speech nibbles in

the common data memory, in the area reserved for that

particular receive slot. Then, during the transmit phase, it

passes the start pointer of the same data memory area to

the transmit block. Thus, the speech data is echoed to the

other user. To handle quality degradation for local calls, a

mute can be performed at the RF side of the speech buffer.

6.5.8

DATA SYNCHRONIZATION (see Fig.10)

The data synchronization is done in 2 phases:

• Bit synchronization

• Sync word detection.

Bit synchronization is done using a Digital PLL (DPLL),

with an oversampling factor of 12, i.e. the DPLL is running

at 12 times the data rate. The output from the DPLL is a

receive clock signal (RxC), which acts as the enable for a

20-bit shift register.

Sync word detection is achieved by checking the incoming

data pattern with the expected synchronization field

pattern, using a correlator.

The correlator has a programmable threshold, so it can

accept bit errors in the sync field pattern up to the

threshold level. Furthermore, the correlator window is

programmable. This means that ‘SlotSync’, which

indicates the slot synchronization event, can be detected

only during a certain period (the time window).

Fig.9 Local call switching on the RF-side.

handbook, full pagewidth

MBH712

Rx1

speech buffers

in data memory

Rx2

Tx1

Tx2

RF slots

Fig.10 Schematic of the receiver synchronization part.

handbook, full pagewidth

MBH713

threshold

base/handset

CORRELATOR

(E98A)

Q0 to Q15

×C

filtered

data in

R_DATA

(1152 kbits/s)

to serial

receiver logic

FILTER

DPLL

13.824 MHz

XOR

20-BIT SHIFT

Q16 to Q19

SlotSync

correlator

window

SYNC

CHECK

(1010)

DPLL_sync

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