PCD5042H datasheet(9/28 Pages) PHILIPS

9 / 28 page

1996 Oct 31

Philips Semiconductors

Objective speciﬁcation

DECT burst mode controller

PCD5042

FUNCTIONAL DESCRIPTION (see Fig.1)

The PCD5042 has dedicated hardware blocks containing

logic for time-critical functions requiring bit or byte-time

accuracy. Other functions requiring only slot-time

accuracy are performed by software in the

Preprogrammed Communication Controller (PCC). This

approach offers maximum flexibility during prototyping.

6.1

Internal bus and data memory

6.1.1

INTERNAL BUS

The function of the internal bus is:

• To provide access for all functional blocks to the

common data memory

• To provide access for the microcontroller-interface and

the PCC to all other functional blocks.

All functional blocks (speech-interface, RF-interface,

microcontroller-interface and PCC) can autonomously use

the internal bus to communicate with the common data

memory.

A bus controller is used to handle the bus priority

mechanism. When several blocks request access

simultaneously, the request with the highest priority is

handled first.

6.1.2

DATA MEMORY

A large part of the data memory is used for the bit rate

adaptation between the DECT radio interface and the

speech interface. The data memory also acts as the main

communication interface between the external

microprocessor and the PCC.

6.2

Clock generation and correction (see Fig.4)

The device has an on-chip 13.824 MHz crystal oscillator.

From this source, a few frequencies are derived for internal

and external use. Frequencies generated for external use

are:

• 13.824 MHz for the synthesizer reference

(pin REF_CLK). This output is only provided if the

synthesizer power-down control (output on

pin S_POWER_DWN) is not selected.

• 0.144 to 13.824 MHz for the microcontroller clock

(pin PROC_CLK)

• 3.456 MHz for the ADPCM CODEC (pin CLK3)

• 1200 Hz (pin 1200_HZ) for dual synthesizer switching

• 100 Hz (pin CLK100) indicates start of frame.

Nominally, the frequency on pin CLK3 is 3.456 MHz. This

frequency is obtained by dividing the crystal frequency by

4. Sometimes, the crystal frequency will be divided by 3

or by 5, to synchronize the combination of the ADPCM

CODEC and the device to an external source. External

synchronization for base station applications is achieved

as follows:

• Master base station. The master base station provides

a 100 Hz signal to slave base stations on pin

SYNCPORT. If the PCD5042 is connected to a digital

interface (32-slot mode speech interface), the external

synchronization will be done on the incoming 8 kHz

signal. If it is connected to an analog line (12-slot mode

speech interface), it will use its own crystal oscillator as

reference.

• Slave base station. The slave base station will use the

incoming SYNCPORT signal as synchronization

reference.

6.3

Programmable communication controller and

program memory

6.3.1

PCC

The PCC is a RISC-type controller and is used to control

functions which are slot-time accurate. It is well suited for

bit manipulation, and runs at a clock frequency of

6.912 MHz (equivalent to 3.4 Mips). After finishing a task,

it switches to a power saving state, from which it returns

after a pre-programmed time.

6.3.2

PCC FUNCTIONS

The most important functions of the PCC are to:

• Perform the appropriate actions on received messages:

PMID and FMID checking, RFPI checking, TBC

handling

• Prepare A-field messages for transmission

• Prepare the RF-interface for the coming slot

• Perform the procedures for RSSI and set-up scan,

maintain scan counters and timers, assemble the RSSI

field in the common data memory

• Filter events and indicate them to the microcontroller by

interrupt.

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