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WM8772SEDS/RV Fiches technique(PDF) 16 Page - Wolfson Microelectronics plc |
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WM8772SEDS/RV Fiches technique(HTML) 16 Page - Wolfson Microelectronics plc |
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16 / 73 page ![]() WM8772EDS – 28 LEAD SSOP Production Data w PD Rev 4.2 October 2005 16 PAGES 12 TO 36 DESCRIBE THE OPERATION OF THE WM8772EDS 28 LEAD SSOP PRODUCT VARIANT. PAGES 37 TO 66 DESCRIBE THE OPERATION OF THE WM8772EFT 32 LEAD TQFP PRODUCT VARIANT. WM8772EDS – 28 LEAD SSOP MASTER CLOCK TIMING MCLK t MCLKL t MCLKH t MCLKY Figure 13 ADC and DAC Master Clock Timing Requirements Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, AGND, DGND = 0V, TA = +25 oC, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT System Clock Timing Information MCLK System clock pulse width high tMCLKH 11 ns MCLK System clock pulse width low tMCLKL 11 ns MCLK System clock cycle time tMCLKY 28 ns MCLK Duty cycle 40:60 60:40 Table 2 Master Clock Timing Requirements DIGITAL AUDIO INTERFACE – MASTER MODE LRC DOUT DIN1/2/3 WM8772 CODEC DSP/ ENCODER/ DECODER 3 BCLK Figure 14 Audio Interface - Master Mode |
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