WM8772SEDSSLASHRV datasheet(57/73 Pages) WOLFSON

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WM8772EFT – 32 LEAD TQFP

PD Rev 4.2 October 2005

POWERDOWN MODES

The WM8772EFT has powerdown control bits allowing specific parts of the WM8772EFT to be

powered off when not being used. Control bit ADCPD powers off the ADC. The three stereo DACs

each have a separate powerdown control bit, DACPD[2:0] allowing individual stereo DACs to be

powered off when not in use. Setting ADCPD and DACPD[2:0] will powerdown everything except the

references VMID and REFADC. These may be powered down by setting PDWN. Setting PDWN will

override all other powerdown control bits. It is recommended that the ADC and DACs are powered

down before setting PDWN.

ZERO DETECT

The WM8772EFT has a zero detect circuit for each DAC channel that detects when 1024

consecutive zero samples have been input. The MUTE pin output may be programmed to output the

zero detect signal (see Table 10) which may then be used to control external muting circuits. A ‘1’ on

MUTE indicates a zero detect. The zero detect may also be used to automatically enable DAC mute

by setting IZD.

DZFM[1:0]

MUTE

All channels zero

Channel 1 zero

Channel 2 zero

Channel 3 zero

Table 21 Zero Flag Output Select

SOFTWARE CONTROL INTERFACE OPERATION

The WM8772EFT is controlled using a 3-wire serial interface in software mode or pin programmable

in hardware mode.

The control mode is selected by the state of the MODE pin.

The control interfaces are 5V tolerant; meaning that the control interface input signals ML/I2S,

MC/IWL and MD/DM may have an input high level of 5V while DVDD is 3V. Input thresholds are

determined by DVDD. MUTE and MODE are also 5V tolerant.

3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE

MD/DM is used for the program data, MC/IWL is used to clock in the program data and ML/I2S is

used to latch the program data. MD/DM is sampled on the rising edge of MC/IWL. The 3-wire

interface protocol is shown in Figure 34.

B15

B14

B13

B12

B11

B10

ML/I2S

MC/IWL

MD/DM

Figure 58 3-Wire SPI Compatible Interface

B[15:9] are Control Address Bits

B[8:0] are Control Data Bits

ML/I2S is edge-sensitive – the data is latched on the rising edge of ML/I2S.

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