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IP101G-DS-R01 Fiches technique(PDF) 60 Page - List of Unclassifed Manufacturers

No de pièce IP101G-DS-R01
Description  Single Port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver
PDF  65 Pages
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Fabricant  ETC [List of Unclassifed Manufacturers]
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IP101G-DS-R01 Fiches technique(HTML) 60 Page - List of Unclassifed Manufacturers

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IP101G
Data Sheet
7.4.3 RMII Timing
a. Transmit Timing Requirements
Table 17 RMII Transmit Timing Requirements
Symbol
Description
Min.
Typ.
Max.
Unit
TRMII_CLK_IN
Period of RMII clock input
-
20±50ppm -
ns
Ts
TXEN, TXD to RMII_CLK_IN setup time
4
-
-
ns
Th
TXEN, TXD to RMII_CLK_IN hold time
2
-
-
ns
Figure 21 RMII Transmit Timing Requirements
b. Receive Timing
Table 18 RMII Receive Timing Specifications
Symbol
Description
Min.
Typ.
Max.
Unit
TRMII_CLK_IN
Period of RMII clock input
-
20±50ppm -
ns
Td
2
RMII_CLK_IN rising edge to RXDV, RXD output
delay when VDDIO is 3.30V.
6
10
13
ns
Td
RMII_CLK_IN rising edge to RXDV, RXD output
delay when VDDIO is 2.50V.
6
10
16
ns
Td
RMII_CLK_IN
RXDV, RXD[3:0]
TRMII_CLK_IN
Figure 22 RMII Receive Timing Specifications
2 Timing was measured for the pin load TXEN and TXD[1:0] of IP101G. The reference 50MHz clock was from
output pin RXCLK/50M_CLKO of IP101G via the default driving current.
60/65
January 14, 2014
Copyright © 2011, IC Plus Corp.
IP101G-DS-R01



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