IP101G-DS-R01 datasheet(36/65 Pages) ETC

36 / 65 page

IP101G

Data Sheet

36/65

January 14, 2014

IP101G-DS-R01

MII page4 register16

page

MII

ROM R/W

Description

Default

16[15]

R/W WOL_PLUS_EN

WOL+ enable function.

Set high to enable WOL+ function.

1=Enable

0=Disable

16[14]

R/W WOL_PLUS_MASTER

WOL+ master mode setting.

This bit is used to select WOL+ either master mode or slave

mode.

1=WOL+ Master mode

0=WOL+ Slave mode

16[13]

R/W INTR_ACT_HIGH

Interrupt active high.

This bit is used to select the active level either high or low of

interrupt pin.

1=Pin "INTR" is set to output type and active high.

0=Pin "INTR" is set to open drain type and active low.

16[12]

R/W Reserved

16[11]

R/W SENSE_MAGIC_PKT

Sense Magic Packet.

Set high to enable WOL+ interrupt when magic packet is

receiving.

1=Enable

0=Disable

16[10]

R/W SENSE_ANY_PKT

Sense Any Packet.

Set high to enable WOL+ interrupt when any good CRC packet

is receiving.

1=Enable

0=Disable

16[9]

R/W SENSE_DUT

Sense DUT.

Set high to enable wake up event detection (magic packet, any

packet) of corresponding port.

1=Enable

0=Disable

16[8]

R/W WOL_PLUS_DNSPD_EN

WOL+ Down Speed Enable.

Set high to enable WOL+ down speed function

1=Enable

0=Disable

16[7:6]

R/W WOL_PLUS_TIMER_SEL

WOL+ Timer Select,

2’b00 = 30 seconds.

2’b01 = 3 minutes.

2’b10 = Reserved for internal test used.

2’b11 = 10 minutes.

2’b01

IP101G-DS-R01 Fiches technique(PDF) 36 Page - List of Unclassifed Manufacturers

IP101G-DS-R01 Fiches technique(HTML) 36 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

Fiches technique Télécharger

Lien URL