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CS43L21 Fiches technique(PDF) 21 Page - Cirrus Logic |
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CS43L21 Fiches technique(HTML) 21 Page - Cirrus Logic |
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21 / 63 page ![]() DS723A1 21 CS43L21 POWER CONSUMPTION See (Note 19) 19. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample rate = 48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode and mas- ter/slave operation. 20. RESET pin 25 held LO, all clocks and data lines are held LO. 21. RESET pin 25 held HI, all clocks and data lines are held HI. 22. VL current will slightly increase in master mode. Power Ctl. Registers Typical Current (mA) Operation 02h 03h V iVA_HP iVA iVD iVL (Note 22) Total Power (mWrms) 1 Off (Note 20) xxxx xxxxxx 1.8 0 0 0 0 0 2.5 0 0 0 0 0 2 Standby (Note 21) xxxx xx1 xxx 1.8 0 0.01 0.02 0 0.05 2.5 0 0.01 0.03 0 0.10 5 Mono Playback 1011 110111 1.8 1.66 1.40 2.35 0.01 9.74 2.5 2.03 1.71 3.48 0.02 18.08 6 Stereo Playback 0011 110111 1.8 2.77 2.05 2.35 0.01 12.93 2.5 3.21 2.50 3.49 0.02 23.02 |
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