CS43L21 datasheet(17/63 Pages) CIRRUS

No de pièce	CS43L21

Description	Low Power, Stereo Digital to Analog Converter

PDF	63 Pages

Scroll/Zoom	100%

Fabricant	CIRRUS [Cirrus Logic]

Site Internet	http://www.cirrus.com

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17 / 63 page

DS723A1

CS43L21

10. After powering up the CS43L21, RESET should be held low after the power supplies and clocks are set-

tled.

11. See “Example System Clock Frequencies” on page 57 for typical MCLK frequencies.

12. See “Master” on page 29

Master Mode (Note 12)

Output Sample Rate (LRCK)

All Speed Modes

-Hz

LRCK Duty Cycle

SCLK Frequency

1/tP

64•Fs

SCLK Duty Cycle

LRCK Edge to SDIN MSB Rising Edge

td(MSB)

SDIN Setup Time Before SCLK Rising Edge

ts(SD-SK)

SDIN Hold Time After SCLK Rising Edge

Parameters

Symbol

Min

Max

Units

ts(SD-SK)

MSB

MSB-1

LRCK

SCLK

SDIN

ts(LK-SK)

Figure 4. Serial Audio Interface Slave Mode Timing

MCLK

128

-----------------

ts(SD-SK)

MSB

MSB-1

LRCK

SCLK

SDIN

td(MSB)

Figure 5. Serial Audio Interface Master Mode Timing

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