10 of 49

January 18, 2011

CPS-10Q

CPS-10Q Datasheet

2010 Integrated Device Technology, Inc. All rights reserved.

Figure 6 AC Output Test Load (I2C)

Note: The SDA and SCL pins are open-drain drivers. Refer to the

Philips I2C specification [1] for appropriate selection of pull-up

resistors for each.

Figure 7 sRIO Lanes Test Load

The characteristic impedance Z0 should be designed for 100 Ohms. An inline capacitor C1 and C2 at each input of the receiver provides AC-coupling

and a DC-block. The IDT recommended and test value is 100nF for each. Thus, any DC bias differential between the two devices on the link is

negated. The differential input resistance at the receiver is designed to be 100 Ohms (per sRIO specification). Thus, R1 and R2 are 50 Ohms each.

Note that VBIAS is the internal bias voltage of the device’s receiver.

SDA,

SCL

400pF (max)

2k Ohm

3.3V / 2.5V

Z0

Z0

Tx

TXP

TXN

Rx

RXP

RXN

Vbias

C1

C2

R1

R2

Internal

To Device