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January 18, 2011

CPS-10Q

CPS-10Q Datasheet

2010 Integrated Device Technology, Inc. All rights reserved.

Signal Definitions

JTAG operations such as Reset, State-transition control and Clock sampling are handled through the signals listed in the table below. A functional

overview of the TAP Controller and Boundary Scan registers is provided in the sections following the table.

Pin Name Type

Description

TRST

Input

JTAG RESET

Asynchronous reset for JTAG TAP controller (internal pull-up)

TCK

Input

JTAG Clock

Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge.

JTAG_TDO is output on the falling edge.

TMS

Input

JTAG Mode Select. Requires an external pull-up.

Controls the state transitions for the TAP controller state machine (internal pull-up)

TDI

Input

JTAG Input

Serial data input for BSC chain, Instruction Register, IDCODE register, and BYPASS

register (internal pull-up)

TDO

Output JTAG Output

Serial data out. Tri-stated except when shifting while in Shift-DR and SHIFT-IR TAP

controller states.

Table 29 JTAG Pin Descriptions