ICS831721AGI REVISION A FEBRUARY 3, 2014

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©2014 Integrated Device Technology, Inc.

ICS831721I Data Sheet

DIFFERENTIAL CLOCK/DATA MULTIPLEXER

The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.

HCSL output driver circuit and termination are shown in Figure 4.

VDD

VOUT

RL

50



IC

IOUT = 17mA

RREF =

475

 ±1%

Figure 4. HCSL Driver Circuit and Termination

HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,

use the following equations which assume a 50

 load to ground.

The highest power dissipation occurs when VDD_MAX.

Power

= (VDD_MAX –VOUT)*IOUT,

since VOUT –IOUT *RL

=(VDD_MA – IOUT *RL)*IOUT

= (3.6V – 17mA * 50

) * 17mA

Total Power Dissipation per output pair = 46.8mW