SN250 datasheet(97/130 Pages) STMICROELECTRONICS

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SN250

Functional description—application modules

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7.4.4

Timer functionality (input capture)

There are two capture registers that store the timer count value on a trigger condition from

GPIO signals. The timer trigger signals TMR1IA and TMR1IB for Timer 1, and TMR2IA and

TMR2IB for Timer 2 are provided by external signals routed to the GPIO pins.

These timer trigger signals are synchronized to the main 12MHz clock, passed to an

optional glitch filter, and followed by an edge detection circuitry.

These functions are controlled by software with the register bits TMR_CAPMOD[1:0], and

TMR_CAPFILT

in the TMR1_CAPCFGA, TMR1_CAPCFGB, TMR2_CAPCFGA, and

TMR2_CAPCFGB

registers.

All glitch filters consist of a flip-flop-driven, 4-bit shift register clocked with the main 12MHz

clock.

7.4.5

Timer interrupt sources

Each timer supports a number of interrupts sources:

●

On overflow during up-count from all 1s to zero.

●

On counter reaching output compare values stored in the TMR1_CMPA, TMR1_CMPB or

TMR2_CMPA

, and TMR2_CMPB registers.

●

On counter reaching zero, TMR1_TOP, or TMR2_TOP.

●

On capturing events from GPIO.

To generate interrupts to the CPU, the interrupt masks in the INT_TMRCFG and INT_CFG

registers must be enabled.

Table 32.

GPIO/Timer trigger conditioning

TMR_CAPMOD[1:0]

Detection Mode

Disabled

Rising Edge

Falling Edge

Either Edge

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