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March 31, 2008

IDT80KSW0004

Datasheet

The EXTEST_PULSE instruction enables edge-detecting behavior on signal paths containing AC pins, where test receivers reconstruct the original

waveform created by a driver even when signals decay due to AC-coupling.

As the operation name suggests, enabling EXTEST_PULSE causes a pulse to be issued which can be detected even on AC-coupled receivers. Refer

to the IEEE Std 1149.6 for full details. Below is a short synopsis.

If enabled, the output signal is forced to the value in its associated Boundary-Scan Register data cell for its driver (true and inverted values for a differ-

ential pair) at the falling edge of TCK in the Update-IR and Update-DR TAP Controller states. The output subsequently transitions to the opposite of

that state (an inverted state) on the first falling edge of TCK that occurs after entering the Run-Test/Idle TAP Controller state. It then transitions back

again to the original state (a noninverted state) on the first falling edge of TCK after leaving the Run-Test/Idle TAP Controller state.

EXTEST TRAIN

This IEEE 1149.6 instruction applies only to the AC-coupled pins. All DC pins will perform as if the IEEE Std 1149.1 EXTEST instruction is operating

whenever the EXTEST_PULSE instruction is effective.

The EXTEST_TRAIN instruction enables edge-detecting behavior on signal paths containing AC pins, where test receivers reconstruct the original

waveform created by a driver even when signals decay due to AC-coupling.

As the operation name suggests, enabling EXTEST_TRAIN causes a pulse train to be issued which can be detected even on AC-coupled receivers.

Once in an enabled state, the train will be sent continously in response to the TCK clock. No other signaling is required to generate the pulse train

while in this state. Refer to the IEEE Std 1149.6 for full details. Below is a short synopsis.

First, the output signal is forced to the state matching the value (a noninverted state) in its associated Boundary-Scan Register data cell for its driver

(true and inverted values for a differential pair), at the falling edge of TCK in update-IR. Then the output signal transitions to the opposite state (an

inverted state) on the first falling edge of TCK that occurs after entering the Run-Test/Idle TAP Controller state. While remaining in this state, the

output signal will continue to invert on every falling edge of TCK, thereby generating a pulse train.

RESERVED

Reserved instructions are not implemented, but default to a BYPASS mode. IDT recommends using the standard BYPASS opcode rather than

RESERVED opcodes if BYPASS functionality is desired.

PRIVATE

Private instructions implement various test modes used in the device manufacturing process. The user should not enable these instructions.

Usage Considerations

As previously stated, there are internal pull-ups on

TRST, TMS, and TDI. However, TCK also needs to be driven to a known value. It is best to either

drive a zero on the TCK pin when it is not being used or to use an external pull-down resistor. In order to guarantee that the JTAG does not interfere

with normal system operation, the TAP controller should be forced into the Test-Logic-Reset controller state by continuously holding

TRST low and/or

TMS high when the chip is in normal operation. If JTAG will not be used, externally pull-down

TRST low to disable it.

JTAG Configuration Register Access

As previously mentioned, the JTAG port may be used to read and write to the CPS-12’s configuration registers. The same JTAG instruction (4b1010)

is used for both writes and reads.