30 of 47

March 31, 2008

IDT80KSW0004

Datasheet

Test Data Register (DR)

The Test Data register contains the following:

◆ The Bypass register

◆ The Boundary Scan registers

◆ The Device ID register

These registers are connected in parallel between a common serial input and a common serial data output, and are described in the following

sections. For more detailed descriptions, refer to IEEE Standard Test Access port (IEEE Std. 1149.1-1990).

Boundary Scan Registers

The CPS-12 boundary scan chain is 46 bits long. The five JTAG pins do not have scan elements associated with them. Full boundary scan details can

be found in the associated BSDL file which may be found on our web site (www.IDT.com). The boundary scan chain is connected between TDI and

TDO when the EXTEST or SAMPLE/PRELOAD instructions are selected. Once EXTEST is selected and the TAP controller passes through the

UPDATE-IR state, whatever value that is currently held in the boundary scan register’s output latches is immediately transferred to the corresponding

outputs or output enables.

Therefore, the SAMPLE/PRELOAD instruction must first be used to load suitable values into the boundary scan cells, so that inappropriate values are

not driven out onto the system pins. All of the boundary scan cells feature a negative edge latch, which guarantees that clock skew cannot cause

incorrect data to be latched into a cell. The input cells are sample-only cells. The simplified logic configuration is shown in the figure below.

Figure 21 Diagram of Observe-only Input Cell

The simplified logic configuration of the output cells is shown in the figure below.

Figure 22 Diagram of Output Cell

Input

Pin

shift_dr

From previous cell

clock_dr

DQ

To next cell

To core logic

Data from Core

Data from Previous Cell

shift_dr

To Next Cell

To Output Pad

clock_dr

update_dr

D

Q

DQ

EXTEST