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C5NPARCH-RM/D Fiches technique(PDF) 89 Page - NXP Semiconductors

No de pièce C5NPARCH-RM/D
Description  C-3e Network Processor Silicon Revision A1
PDF  114 Pages
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Fabricant  NXP [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo NXP - NXP Semiconductors

C5NPARCH-RM/D Fiches technique(HTML) 89 Page - NXP Semiconductors

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AC Timing Specifications
89
03
MDIO Serial Interface Timing Specifications
The MDIO serial interface timing is shown in Figure 20 and described in Table 45.
Figure 20 MDIO Serial Interface Timing Diagram
Cycle 2
Cycle 3
Cycle 4
Tsic
Tsids
SICL
SIDA
(output)
SIDA
(input)
Tsods Tsodh
Table 45 MDIO Serial Interface Timing Description
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
Tsic
SICL Cycle Time
40
ns
Tsids
SIDA Input Setup
10
ns
Tsidh
SIDA Input Hold
0.0
ns
Tsods
SIDA Output Setup
10
ns
Tsodh
SIDA Output Hold
10
ns
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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