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MPC855T Fiches technique(PDF) 59 Page - NXP Semiconductors

No de pièce MPC855T
Description  MPC860 PowerQUICC Family Hardware Specifications
PDF  77 Pages
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Fabricant  NXP [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPC855T Fiches technique(HTML) 59 Page - NXP Semiconductors

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MPC860 PowerQUICC Family Hardware Specifications, Rev. 10
Freescale Semiconductor
59
CPM Electrical Characteristics
Figure 61. Ethernet Transmit Timing Diagram
Figure 62. CAM Interface Receive Start Timing Diagram
Figure 63. CAM Interface REJECT Timing Diagram
TCLK1
128
TxD1
(Output)
128
TENA(RTS1)
(Input)
Notes:
Transmit clock invert (TCI) bit in GSMR is set.
If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the CSL bit is set in
the buffer descriptor at the end of the frame transmission.
1.
2.
RENA(CD1)
(Input)
133
134
132
131
121
129
(Note 2)
RCLK1
RxD1
(Input)
RSTRT
(Output)
0
136
125
1
1
BIT1
BIT2
Start Frame Delimiter
REJECT
137



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