MIC2133 datasheet(19/50 Pages) MICROCHIP

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DS20006653B-page 19

MIC2133

FIGURE 4-1:

Steady-State Operation (FB

Ripple Shows Injected and ESR Ripple Only,

Reactive Impedances Neglected).

Figure 4-2 shows the operation of the MIC2133 during

load transient. The output voltage drops due to the sud-

den load increase, which causes the VFBS to decrease

and the output voltage of the gm amplifier, Vgm, to be

less than VREF_COM. This will cause the error compar-

ator to trigger an on-time period. At the end of the

on-time period, a Minimum Off-Time, TOFF(MIN), is gen-

erated to charge CBST because the feedback voltage is

still below VREF. Then, the next on-time period is trig-

gered and applies DMAX due to the low feedback volt-

age. Therefore, the switching frequency changes

during the load transient to deliver DMAX and zero duty

cycle when the high-current load disappears for both

phases, but returns to the nominal fixed frequency

once the output has stabilized at the new load current

level. With the varying duty cycle and switching fre-

quency, the output recovery time is fast and the output

voltage deviation is small in the MIC2133 converter.

The phases will overlap during load transient until the

output voltage error is corrected. The transient

response is shown in Figure 4-3.

FIGURE 4-2:

MIC2133 Load Transient

Response Timing.

FIGURE 4-3:

MIC2133 Load Transient

Response.

Unlike true Current-mode control, the MIC2133 uses

the output voltage ripple to trigger an on-time period.

The output voltage ripple is proportional to the inductor

current ripple if the ESR of the output capacitor is large

enough. To meet the stability requirements, the

MIC2133 feedback voltage ripple must be in phase with

the inductor current ripple, and large enough to be

sensed by the gm amplifier and the error comparator.

The recommended feedback voltage ripple is 20 mV ~

100 mV. If a low-ESR output capacitor is selected, then

the feedback voltage ripple may be too small to be

sensed by the gm amplifier and the error comparator.

Also, the output voltage ripple and the feedback volt-

age ripple are not necessarily in phase with the induc-

tor current ripple if the ESR of the output capacitor is

very low. In these cases, ripple injection is required to

ensure proper operation.

IOUT= IL1+ IL2

VOUT(PP)=ESRCOUT X

IO(PP)

VOUT

Vgm

VREF_COM

VDH1

VDH2

TRIGGER ON TIME IF Vgm IS BELOW VREF_COM

ESTIMATED ON TIME

IO(PP)

IOUT

PHASE 2

PHASE 1

RIP_INJ

IL(PP)

VFB(PP)

IL1, IL2

FULL LOAD

IOUT

VOUT

Vgm

VREF_COM

VDH

TOFFMIN

NO LOAD

DMAX

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