M25PE20 datasheet(24/37 Pages) STMICROELECTRONICS

24 / 37 page

M25PE10, M25PE20

24/37

POWER-UP AND POWER-DOWN

At Power-up and Power-down, the device must

not be selected (that is Chip Select (S) must follow

the voltage applied on VCC) until VCC reaches the

correct value:

–VCC(min) at Power-up, and then for a further

delay of tVSL

–VSS at Power-down

Usually a simple pull-up resistor on Chip Select (S)

can be used to ensure safe and proper Power-up

and Power-down.

To avoid data corruption and inadvertent write op-

erations during power up, a Power On Reset

(POR) circuit is included. The logic inside the de-

vice is held reset while VCC is less than the Power

On Reset (POR) threshold value, VWI – all opera-

tions are disabled, and the device does not re-

spond to any instruction.

Moreover, the device ignores all Write Enable

(WREN), Page Write (PW), Page Program (PP),

Page Erase (PE) and Sector Erase (SE) instruc-

tions until a time delay of tPUW has elapsed after

the moment that VCC rises above the VWI thresh-

old. However, the correct operation of the device

is not guaranteed if, by this time, VCC is still below

VCC(min). No Write, Program or Erase instructions

should be sent until the later of:

–tPUW after VCC passed the VWI threshold

–tVSL after VCC passed the VCC(min) level

These values are specified in Table 7.

If the delay, tVSL, has elapsed, after VCC has risen

above VCC(min), the device can be selected for

READ instructions even if the tPUW delay is not yet

fully elapsed.

As an extra protection, the Reset (Reset) signal

could be driven Low for the whole duration of the

Power-up and Power-down phases.

At Power-up, the device is in the following state:

–

The device is in the Standby Power mode (not

the Deep Power-down mode).

–

The Write Enable Latch (WEL) bit is reset.

Normal precautions must be taken for supply rail

decoupling, to stabilize the VCC supply. Each de-

vice in a system should have the VCC rail decou-

pled by a suitable capacitor close to the package

pins. (Generally, this capacitor is of the order of

0.1 µF).

At Power-down, when VCC drops from the operat-

ing voltage, to below the Power On Reset (POR)

threshold voltage, VWI, all operations are disabled

and the device does not respond to any instruc-

tion. (The designer needs to be aware that if a

Power-down occurs while a Write, Program or

Erase cycle is in progress, some data corruption

can result.)

Figure 20. Power-up Timing

VCC

AI04009C

VCC(min)

VWI

Reset State

of the

Device

Chip Selection Not Allowed

Program, Erase and Write Commands are Rejected by the Device

tVSL

tPUW

time

Read Access allowed

Device fully

accessible

VCC(max)

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