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STA335BWSQS Fiches technique(PDF) 44 Page - STMicroelectronics |
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STA335BWSQS Fiches technique(HTML) 44 Page - STMicroelectronics |
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44 / 70 page ![]() Register description STA335BWSQS 44/70 6.8 AutoMode registers (addr 0x0B and 0x0C) 6.8.1 AutoMode register 1 (address 0x0B) AMGC[1:0], in conjunction with AMGC[3:2] defined in register 0x31, defines anti-clipping and DRC presets. Using AMGC[3:0] bits, attack and release thresholds and rates are automatically configured to properly fit application specific configuration. 6.8.2 AutoMode register 2 (address 0x0C) …… 11010111 (0xD7) -59.5 dB 11011000 (0xD8) -60 dB 11011001 (0xD9) -61 dB 11011010 (0xDA) -62 dB …… 11101100 (0xEC) -80 dB 11101101 (0xED) Hard channel mute …… 11111111 (0xFF) Hard channel mute Table 53. Channel volume as a function of CxV[7:0] (continued) CxV[7:0] Volume D7 D6 D5 D4 D3 D2 D1 D0 Reserved AMGC1 AMGC2 Reserved 00 Table 54. AutoMode gain compression/limiters selection AMGC[1:0] Mode 00 User programmable GC 01 AC no clipping 2.1 10 AC limited clipping (10%) 2.1 11 DRC nighttime listening mode 2.1 D7 D6 D5 D4 D3 D2 D1 D0 XO3 XO2 XO1 XO0 AMAM2 AMAM1 AMAM0 AMAME 00 00 000 0 |
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