ZSSC3123AI2R datasheet(10/62 Pages) RENESAS

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ZSSC3123 Datasheet

Nov 19, 2021

Page 10

5. Electrical Characteristics

Table 4.

Electrical Characteristics

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Units

Supply Current

IDD

Update Mode Current (varies with

part configuration) [a]

Best case settings: [b]

Mult 1, 8-bit, 125ms Power Down

100

μA

Worst case settings:

Mult 1, 14-bit, 0ms Power Down

750

1100

IPDM

Extra Current with PDM enabled [b]

150

μA

ISLEEP

Sleep Mode Current [a]

-40 to 85°C

0.6

μA

-40 to 125°C

μA

Voltage Levels

VPOR

Power-On-Reset Level

1.6

1.7

2.2

VREG

Active Regulated Voltage

Note: Regulated voltage can be

measured on the Vcore pin.

2.4

2.55

2.7

Capacitance-to-Digital Converter (CDC)

RESCDC

Resolution

Bits

fMULT1

Excitation Frequency of External

Capacitances C0 and C1

(for a system frequency fSYS)

Mult 1

fSYS/2

kHz

fMULT2

Mult 2

fSYS/4

kHz

fMULT4

Mult 4

fSYS/8

kHz

fMULT8

Mult 8

fSYS/16

kHz

INLCDC

Integral Nonlinearity (INL) [c]

Mult 1, 10% to 90% input, 14-bit

0.2

DNLCDC

Differential Nonlinearity (DNL) [b]

Mult 1, 10% to 90% input, 14-bit

0.9

LSB

EEPROM

nWRI_EEP

Number of Erase/Write Cycles

At 85

C

100k

tWRI_EEP

Data Retention

At 100

C

Year

Temperature Conversion

RESTEMP

Resolution in °C [b]

-40 to 125°C, 8-bit mode

0.64

0.96

1.6

°C

-40 to 125°C, 14-bit mode

0.01

0.015

0.025

INLCDC

Nonlinearity First Order Fit [b], [d]

-40 to 125°C

±0.5

±1

°C

INLCDC

Nonlinearity Second Order Fit [b], [e] -40 to 125°C

±0.2

±0.4

°C

PSRTEMP

Voltage Dependency [b]

VSUPPLY > VREG+0.25V

0.03

0.1

°C/V

2.3V ≤ VSUPPLY ≤ VREG + 0.25V

1.25

2.25

PDM Output

VPDM_Range

Output Range [b]

%VSUPPLY

fPDM

PDM Frequency

fSYS/8

kHz

tSETT

Filter Settling Time [b], [f]

0% to 90% LP filter 10k

/400nF

9.2

VRIPP

Ripple [b], [f]

0% to 90% LP filter 10k

/400nF

1.0

mV/V

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