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7.

Functional diagram

Fig 1.

Functional diagram P60D080/P60D144

001aam548

RF

INTERFACE

LA

LB

IO1

IO3

PROGRAMMABLE

I/O 1, 2, 3

IO2

CLK

RST_N

VDD

VSS

CIU

ISO 14443

ROM

384 KB

PROGRAM MEMORY

SECURE SmartMX2 CPU

EEPROM

80 KB/144 KB

DATA AND PROGRAM

MEMORY

CRC

16 or 32-bit

FAST

RNG

TIMERS

16-bit

T0

16-bit

T1

RAM

AES

COPROCESSOR

TRIPLE-DES

COPROCESSOR

UART

ISO 7816

CLOCK

FILTER

SECURITY SENSORS

RESET GENERATION

VOLTAGE REGULATOR

MEMORY MANAGEMENT UNIT (MMU)

CLOCK

GENERATION

P60D080 P60D144

SYMMETRIC BLOCK CIPHER

INTERFACE

COPY

MACHINE

COPY

MACHINE

WATCHDOG

TIMER

FAME2

ENHANCED

PUBLIC KEY

COPROCESSOR

e.g. RSA, ECC

5632 B

DATA MEMORY

2688 B

DATA MEMORY