SMX2_FAM_P60D080_D144_SDS

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Objective short data sheet

PUBLIC

Rev. 1 — 1 September 2010

197210

4 of 12

NXP Semiconductors

P60D080 and P60D144

Secure high-performance dual interface smart card controller

3.2 Security features

Outstanding Glue Logic chip layout approach:

Most efficient and proven protection against reverse engineering

Based on avoidance of any logical layout block recognition

Secure Fetch (Code and Data)

Active and dynamic shielding

Enhanced security sensors:

Low and high clock frequency sensor

Low and high temperature sensor

Low and high supply voltage sensor

Single Fault Injection (SFI) attack detection

Light sensors (included integrated memory light sensor functionality)

Electronic fuses for safeguarded mode control

Clock input filter for protection against spikes

Power-up and power-down reset

Memory security (encryption and physical measures) for RAM, EEPROM and ROM

Memory Management Unit (MMU) including memory protection:

Secure multi application operating systems via two different operation modes:

System mode and User mode

OS controlled access restriction mechanism to peripherals in User mode

Memory mapping up to 8-MB code memory

Memory mapping up to 8-MB data memory

Built-in integral concept for secure code execution covering code fetch, MMU and CPU

Optional disabling of ROM read instructions by code executed in EEPROM

Optional disabling of any code execution out of RAM

Optional Unique ID for each die

Optional programmable card disable feature

EEPROM programming:

Hardware sequencer controlled

Enhanced error correction mechanism

128-B or 264-B EEPROM for customer-defined Security FabKey:

Featuring batch, wafer or die-individual security data

Encrypted diversification features available on request

14 B user write protected security area in EEPROM (byte access, inhibit functionality

per byte)

32 B write once protected security area in EEPROM (bit access)

32 B user read only protected security area in EEPROM (byte access)

Total useable EEPROM for customer OS (including optional FabKey areas) and

excluding the MIFARE Plus and DESFire EV1 implementations

P60D080: 81408 bytes + above 78 bytes within protected security area

P60D144: 146944 bytes + above 78 bytes within protected security area

Customer specific EEPROM initialization available