SMX2_FAM_P60D080_D144_SDS

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Objective short data sheet

PUBLIC

Rev. 1 — 21 October 2010

198210

3 of 12

NXP Semiconductors

P60C080 and P60C144

Secure high-performance contact interface smart card controller

3.

Features and benefits

3.1 Product specific features

EEPROM: choice of 80 KB or 144 KB

Data retention time: 25 years minimum

Endurance: 500000 cycles

Versatile EEPROM programming: 1 B to 256 B at a time

ROM: 384 KB

RAM: 8.125 KB (8320 B)

5632 B CXRAM (including 256 B IRAM) usable for CPU

2688 B FXRAM usable for Fame2 or CPU

SmartMX2 CPU

orthogonal instruction set offering 32-/24-/16-/8-bit instructions optimized for

secured and low power smart card applications

Enhanced high-performance secured Public Key Infrastructure (PKI) coprocessor

(RSA, ECC) Fame2

Enhanced high-performance secured hardware support for symmetric block cipher

(SBC) algorithms

Secured dual/triple-DES coprocessor

Secured AES coprocessor

Multiple key and data register sets supporting parallel data/key loading and

calculation

True Random Number Generator (compliant to AIS-31)

16-bit and 32-bit CRC coprocessor supporting fast memory verify functionality

Memory Management Unit (MMU)

16 segment cache entries and performance improvements

supporting integral concept for secure code fetch and execution

Copy Machines offering data transfer between all Special Function Registers and all

memory instances without CPU interaction

Watchdog Timer supporting secure code execution

Time Stamp Counter, Real Time Clock

ISO/IEC 7816 contact interface (UART)

ISO/IEC 7816 contact interface (UART) offering hardware support

for ISO/IEC 7816 T=0 and T=1 protocol stack implementation

Hardware support for automatic WTX generation for both ISO/IEC 7816 UART

continuos operation from 1.62 V up to 5.5 V supported

−25 °C to +85 °C ambient temperature