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PI3DPX1202A2ZBEX Fiches technique(PDF) 13 Page - Diodes Incorporated |
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PI3DPX1202A2ZBEX Fiches technique(HTML) 13 Page - Diodes Incorporated |
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13 / 51 page ![]() A product Line of Diodes Incorporated 13 of 51 www.diodes.com February 2020 © Diodes Incorporated PI3DPX1202A Document number: DS40115 Rev 3-3 PI3DPX1202A 4.2 Function Description Power up operation Timing After ENABLE signal is properly set, power up timing sequence complete. ENABLE signal from controller must be LOW until power supply become stable. >100µS Delay time for POR/Bandgap circuit ready <10mS Ramp-up time >400mS Power Supply ENABLE Signal Output 10% 90% Normal Operation Figure 4-2: Power up timing Sequence 3.3V POR Bandgap 3.3V 1.2V Regulator 1.2V POR 1.2V State Machine 3.3V HPD Bu er Level shifter 1.2V Local oscillator HPD_SINK HPD_SRC Reset Power Supply Figure 4-3: Internal power up timing sequence |
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