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STM32WL55JC Fiches technique(PDF) 83 Page - STMicroelectronics

No de pièce STM32WL55JC
Description  Multiprotocol LPWAN dual core 32-bit Arm® Cortex®-M4/M0 LoRa®, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
PDF  147 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32WL55JC Fiches technique(HTML) 83 Page - STMicroelectronics

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Table 39. Typical current consumption in Run and LPRun modes on CPU1, with different codes
running from Flash memory, ART enable (cache ON, prefetch OFF)
Symbol
Parameter
Conditions
Typ
Unit
Typ
Unit
-
Voltage scaling
Code
25 °C
25 °C
IDD(Run)
Supply current in
Run mode
fHCLK = fMSI
All peripherals disabled
Range 2
fHCLK = 16 MHz
Reduced code
1.90
mA
118.75
µA/MHz
CoreMark(1)
1.85
115.63
Dhrystone 2.1
1.85
115.63
Fibonacci
1.80
112.50
While(1)
1.60
100.00
SMPS
Range 2
fHCLK = 16 MHz
Reduced code
1.45
90.63
CoreMark(1)
1.40
87.50
Dhrystone 2.1
1.40
87.50
Fibonacci
1.40
87.50
While(1)
1.30
81.25
Range 1
fHCLK = 48 MHz
Reduced code
5.70
118.75
CoreMark(1)
5.55
115.63
Dhrystone 2.1
5.50
114.58
Fibonacci
5.40
112.50
While(1)
4.65
96.88
SMPS
Range 1
fHCLK = 48 MHz
Reduced code
3.50
72.92
CoreMark(1)
3.40
70.83
Dhrystone 2.1
3.40
70.83
Fibonacci
3.30
68.75
While(1)
2.90
60.42



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