ADP5073

Data Sheet

Rev. A | Page 6 of 17

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SW 1

SLEW 2

PWRGD 3

SYNC/FREQ 4

12 PVIN

11 VREG

10 GND

9

VREF

NOTES.

1. NIC = NO INTERNAL CONNECTION. FOR IMPROVED THERMAL

PERFORMANCE, CONNECT THESE PINS TO THE PCB GROUND PLANE.

2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND.

ADP5073

TOP VIEW

(Not to Scale)

Figure 2. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

SW

Switching Node for the Inverting Regulator.

2

SLEW

Driver Stage Slew Rate Control. The SLEW pin sets the slew rate for the FET driving the SW pin. For the fastest

slew rate (best efficiency), leave the SLEW pin open. For a normal slew rate, connect the SLEW pin to VREG. For

the slowest slew rate (best noise performance), connect the SLEW pin to GND.

3

PWRGD

Power-Good Output (Open-Drain). Pull this pin up to VREG with a resistor to provide a high output when power

is good.

4

SYNC/FREQ

Frequency Setting and Synchronization Input. To set the switching frequency to 2.4 MHz, pull the SYNC/FREQ pin

high. To set the switching frequency to 1.2 MHz, pull the SYNC/FREQ pin low. To synchronize the switching

frequency, connect the SYNC/FREQ pin to an external clock.

5

SS

Soft Start Programming. Leave the SS pin open to obtain the fastest soft start time. To program a slower soft

start time, connect a resistor between the SS pin and GND.

6

EN

Inverting Regulator Precision Enable. The EN pin is compared to an internal precision reference to enable the

inverting regulator output.

7

COMP

Error Amplifier Compensation for the Inverting Regulator. Connect the compensation network between this pin

and GND.

8

FB

Feedback Input for the Inverting Regulator. Connect a resistor divider between the negative side of the

inverting regulator output capacitor and VREF to program the output voltage.

9

VREF

Inverting Regulator Reference Output. Connect a 1.0 μF ceramic filter capacitor between the VREF pin and GND.

10

GND

Ground.

11

VREG

Internal Regulator Output. Connect a 1.0 μF ceramic filter capacitor between the VREG pin and GND.

12

PVIN

Power Input for the Inverting Regulator.

13

AVIN

System Power Supply for the ADP5073.

14, 15, 16

NIC

No Internal Connection. For improved thermal performance, connect these pins to the PCB ground plane.

EPAD

EPAD

Exposed Pad. Connect the exposed pad to GND.