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ZLP12840 Fiches technique(PDF) 42 Page - Zilog, Inc. |
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ZLP12840 Fiches technique(HTML) 42 Page - Zilog, Inc. |
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42 / 58 page ![]() PS024406-0106 P R E L I M I N A R Y Register File ZLP12840 OTP MCU Product Specification 31 Figure 9. Register File 8-Bit Banked Address Map F0hFFh CPU Control F0hFFh CPU Control Ports 00h03h General Registers CPU Control F0hFFh 04hEFh Purpose CPU Control F0hFFh CPU Control F0hFFh Bank 0 Banks 13 Bank 0 Peripheral 00h0Fh Bank D Control Bank 0 Peripheral 00h0Fh Bank F Control = Bank-Independent Address (Always Accesses Bank 0) General Registers 04hEFh Purpose CPU Control F0hFFh Ports 00h03h General Purpose Registers 10hEFh General Purpose Registers 10hEFh * Compilers default interrupt service routine working registers. Not to Scale |
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