DP8496 datasheet(13/92 Pages) NSC

13 / 92 page

40 Functional Description (Continued)

The Processor Interface bus timing can be asynchronous to

any clock on the DP84967

42 BUFFER MEMORY INTERFACE

All data transfers to and from the disk and to and from the

SCSI bus go through buffer memory Buffer memory is at-

tached directly to the Buffer Memory Interface Access by

the DP84967 to buffer memory is performed via the inter-

nal DMA controller All access to the buffer memory is priori-

tized and arbitrated through the DP84967 Thus concur-

rent disk SCSI and processor accesses to the buffer mem-

ory are allowed In normal operation no other bus masters

access the buffer memory

The user has the option of configuring the memory in a byte-

wide or word-wide arrangement If byte wide SRAM or any

type of DRAM is used no components other than the mem-

ory chips are necessary on the buffer memory interface

The only external component that may be needed is an 8-bit

address demultiplexing latch if word-wide SRAM is used

Appropriate buffer memory configuration must be specified

in the setup registers Setup 1 and Setup 2 before proper

chip operation can begin Setup 1 register is used to config-

ure the port timing to static or dynamic modes program the

optional wait states specify the DRAM depth and data bus

width and to enable fast page mode DRAM control Setup 2

421 Static RAM

In SRAM mode there are 19 address bits available to sup-

port up to 512 kBytes in byte mode or 1 MBytes in word

mode There is a large degree of flexibility of SRAM configu-

rations that may be interfaced to the Buffer Memory Inter-

face The specific pins that are used in byte mode are de-

scribed in Table 42 The address bits 19 20 and 21 still

exist in all pointer registers but they are not output to the

interface

TABLE 42 SRAM Address Pins 8-Bit Interface

ADB2

AB4

AB3

Pins 765432102 1076543210

Addr 18 17 16 15 14 13 12 11 109876543210

Bit

SRAM used word-wide can transfer a little less than twice

as fast as byte-wide given equal clock rates The address

increments by two in word mode making address bit 1 of the

pointers the least significant address bit presented on the

physical interface The processor will still access the RAM

as individual upper and lower bytes of a single word by using

address bit 0 in the Processor Pointer A0 will determine

which byte is present in the Buffer Memory Data register

low byte or high byte

The specific pins that are used in word mode are described

in Table 43 The ADSo pin is used to strobe an external 8-

bit latch capturing A12 – 19 so the ADB2 bus can be used

for bi-directional data during the remainder of the memory

cycle

TABLE 43 SRAM Address Pins 16-Bit Interface

ADB2 (MUXed)

AB4

AB3

Pins 7

54321021 0 7 6543210

Addr 19 18 17 16 15 14 13 12 11 10 9 8 7654321

Bit

422 Dynamic RAM

Since dynamic RAMs contain their own address latches no

external latches are needed in byte- or word-wide mode

Multiplexed row and column addresses are issued on the 11

physical address lines of AB3 and AB4 with the least signifi-

cant address bits being issued on the CAS strobe A full

4 MB address range is available in byte wide mode which

can be apportioned on 64k 256k 1M or 4M by n-bit bound-

aries A full 2M address range is available in word wide

mode which can be apportioned on 64k 256k or 1M by

n-bit boundaries

The specified pins that are used in byte mode are described

in Table 44 The specific pins that are used in word mode

are described in Table 45 The redundant signals on AB4

may be ignored

TABLE 44 DRAM Address Pins 8-Bit Interface

Addr

Strobe

AB4

AB3

Depth

64k

RAS

21 19 17 15 14 13 12 11 10 9

CAS

10 9876543210

256k

RAS

21 19 17 15 14 13 12 11 10 9 16

CAS

10 9876543210

RAS

21 19 17 15 14 13 12 11 10 18 16

CAS

10 9876543210

RAS

21 19 17 15 14 13 12 11 20 18 16

CAS

10 9876543210

TABLE 45 DRAM Address Pins 16-Bit Interface

Addr

Strobe

AB4

AB3

Depth

64k

RAS

X 201816151413121110 9

CAS

11 10 9

256k

RAS

X 20 18 16 15 14 13 12 11 10 17

CAS

11 10 9

RAS

X 20181615141312111917

CAS

11 10 9

RAS

X 20181615141312211917

CAS

11 10 9

Note

The address signal x will always be equal to VDD

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