ADRF5250BCPZ-R7 datasheet(11/15 Pages) AD

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Data Sheet

ADRF5250

Rev. 0 | Page 11 of 15

THEORY OF OPERATION

The ADRF5250 requires a positive supply voltage applied to

the VDD pin and 0 V or −3.3 V supply voltage applied to the

VSS pin. Bypass capacitors are recommended on the supply and

digital control lines to minimize RF coupling. An incorporated

negative supply generator is enabled or disabled depending on

the applied VSS supply voltage. Table 4 describes the operation

mode of that negative supply generator.

Table 4. Negative Voltage Generator Operation Mode

VSS

Test Conditions/Comments

0 V

The incorporated negative voltage generator is

enabled

−3.3 V

The incorporated negative voltage generator is

disabled

The ADRF5250 is internally matched to 50 Ω at the RF common

port (RFC) and the RF throw ports (RF1 to RF5); therefore, no

external matching components are required. All of the RF ports

are dc-coupled to 0 V, and no dc blocking is required at the RF

ports when the RF line potential is equal to 0 V. The design is

bidirectional; the RF input signal can be applied to the RFC port

while the RF throw port (RF1 to RF5) is output, or vice versa.

The ADRF5250 has a 3-bit, 1.8 V logic-compatible control

interface that is controlled through the V1, V2, and V3 digital

control voltage pins. A small bypassing capacitor is recommended

on these digital signal lines to improve the RF signal isolation.

The V1 and V3 test points correspond to the LSB and MSB of

the digital control interface of the ADRF5250. The modes of the

RF paths are determined as shown in Table 5.

When an RF path is on, the RF signal is conducted equally well in

both directions between its throw port (RFx) and common port

(RFC). Otherwise, each RFx path is terminated to an internal

50 Ω resistor that provides high loss between the insertion loss

path and its throw ports.

Table 5. Control Voltage Truth Table

Mode

Low

All Off

Low

High

RF1 on

Low

High

Low

RF2 on

Low

High

RF3 on

High

Low

RF4 on

High

Low

High

RF5 on

High

Low

All off

High

All off

The ideal power-up sequence is as follows:

1. Power up GND.

2. Power up VDD and VSS. The relative order is not

important.

3. Power up the digital control inputs. The relative order of

the logic control inputs is not important. However,

powering the digital control inputs before the VDD supply

can inadvertently forward bias and damage the internal

ESD protection structures.

4. Apply an RF input signal.

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