MC56F81663VLC datasheet(63/73 Pages) NXP

63 / 73 page

Table 35. SPI timing (continued)

Characteristic

Symbol

Min

Max

Unit

See Figure

Master

Slave

—

Figure 17

Figure 18

Figure 19

Enable lead time

Master

Slave

tELD

—

Figure 19

Enable lag time

Master

Slave

tELG

—

Figure 19

Clock (SCK) high time

Master

Slave

tCH

—

Figure 16

Figure 17

Figure 18

Figure 19

Clock (SCK) low time

Master

Slave

tCL

—

Figure 19

Data set-up time required for inputs

Master

Slave

tDS

—

Figure 16

Figure 17

Figure 18

Figure 19

Data hold time required for inputs

Master

Slave

tDH

—

Figure 16

Figure 17

Figure 18

Figure 19

Access time (time to data active

from high-impedance state)

Slave

—

Figure 19

Disable time (hold time to high-

impedance state)

Slave

—

Figure 19

Data valid for outputs

Master

Slave (after enable edge)

tDV

—

Figure 16

Figure 17

Figure 18

Figure 19

Data invalid

Master

Slave

tDI

—

Figure 16

Figure 17

Figure 18

Figure 19

Rise time

Figure 16

Table continues on the next page...

PWMs and timers

MC56F81xxx, Rev. 1.1, 12/2020

NXP Semiconductors

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