MTC20454

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DIGITAL INTERFACE

Control Interface

The digital code setting for the MTC20454 configuration is sent over a serial line (CTRLIN) using the word

clock (CLWD). The data burst is composed of 16 bits from which the first bit is used as start bit (‘0’), the

three LSBs being used to identify the data contained in the 12 remaining bits. Test related data are latched

but they are overruled by the normal settings if the TEST pin is low.

Control Interface Timing

The control interface bits are considered valid on each positive edge of the master clock (CLKM). They

will be sampled at this moment. The stop bit will trigger the internal data validation.

The timing requirements are depicted in the following figure and table:

Table 1. Control interface timing requirements

Figure 7. Control interface chronodiagram

Symbol

Parameter

Min

Typ

Max

Remarks

Ts

Setup time

0.5 ns

-

-

Th

Hold time

0.2 ns

-

-

Tdv

Data valid

0.5 ns

-

4 ns

CTRLIN

Start

bit

ctrl cmd

bits

Ts

Th

Tdv

CLKM

CLKWD

1 stop

bit (high)