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AM652X Fiches technique(PDF) 201 Page - Texas Instruments

No de pièce AM652X
Description  Processors Silicon Revision 1.0
PDF  277 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

AM652X Fiches technique(HTML) 201 Page - Texas Instruments

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ASP15
ASP14
ASP13
ASP13
ASP12
ASP12
ASP11
ASP10
ASP10
ASP9
A0
A1
B0
B1
A30 A31
B30 B31 C0
C1 C2 C3
C31
ASP13
ASP13
ASP13
ASP13
ASP13
MCASP[x]_ACLKR/X (Falling Edge Polarity)
MCASP[x]_AHCLKR/X (Rising Edge Polarity)
MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay)
MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay)
MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay)
MCASP[x]_AXR[x] (Data Out/Transmit)
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)
(A)
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)
(B)
201
AM6548, AM6528, AM6546
AM6526, AM6527
www.ti.com
SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019
Submit Documentation Feedback
Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527
Specifications
Copyright © 2017–2019, Texas Instruments Incorporated
A.
For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP
receiver is configured for rising edge (to shift data in).
B.
For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP
receiver is configured for falling edge (to shift data in).
Figure 5-65. MCASP Output Timing
(1) x in MCASP[x]_* is 0, 1 or 2
For more information, see section Controller Area Network (MCAN) in the device TRM.
5.9.5.15 MCSPI
For more details about features and additional description information on the device Serial Port Interface,
see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed
Description.
5.9.5.15.1 SPI—Master Mode
Table 5-66, Figure 5-66 and Figure 5-67 present Timing Requirements for SPI - Master Mode.



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