AM652X datasheet(197/277 Pages) TI1

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I25

I23

I19

I18

I22

I27

I20

I21

I17

I18

I28

Stop

Start

Repeated

Start

Stop

I2C[x]_SDA

I2C[x]_SCL

I16

I26

I24

197

AM6548, AM6528, AM6546

AM6526, AM6527

www.ti.com

SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Specifications

NOTE

I2C emulation is achieved by configuring the LVCMOS buffers to output HiZ instead of

driving high when transmitting logic-1.

Figure 5-63. I2C Transmit Timing(1)

(1) x in I2Cx_SDA and I2Cx_SCL is 0, 1 or 2.

For more information, see section Inter-Integrated Circuit (I2C) Interface in the device TRM.

5.9.5.13 MCAN

For more details about features and additional description information on the device Controller Area

Network Interface, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6,

Detailed Description.

Table 5-63 presents timing parameters for MCANi Interface.

Table 5-63. MCAN Register to Pin Timings

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tp(MCANi_TX)

Delay Time Max, Transmit Shift Register to MCANi_TX pin

Normal

tp(MCANi_RX)

Delay Time Max, MCANi_RX pin to receive shift register

Normal

(1) i in MCANi_* = 0 or 1.

For more information, see section Controller Area Network (MCAN) in the device TRM.

5.9.5.14 MCASP

For more details about features and additional description information on the device Multichannel Audio

Serial Port, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed

Description.

Table 5-64, and Figure 5-64 present timing requirements for MCASP0 to MCASP2.

Table 5-64. Timing Requirements for MCASP(1)

NO.

PARAMETER

DESCRIPTION

Mode

MIN

MAX

UNIT

ASP1

tc(AHCLKRX)

Cycle time, AHCLKR/X

ASP2

tw(AHCLKRX)

Pulse duration, AHCLKR/X high or low

0.5P - 2.5

(2)

ASP3

tc(ACLKRX)

Cycle time, ACLKR/X

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