MP3275AE datasheet(9/16 Pages) EXAR

9 / 16 page

MP3275

Rev. 4.00

Figure 3. Load Circuit for Data

Access Time Test

a. High-Z to VON

DB N

b. High-Z to VOL

+5 V

Figure 4. Load Circuit for

Bus Relinquish Time Test

10pF

a. VON to High-Z

10pF

b. VOL to High-Z

+5 V

Figure 5. Load Circuit for WR to STS Delay

DGND

STL, STS

Serial Data Output

The serial data output sequence is MSB (DB11) first to LSB

(DB0) last. The MSB (DB11) data bit appears at SDO when STS

goes low. The second most significant bit appears at SDO on

the SDC high-to-low transition next. The LSB (DB0) is present

at SDO on the 11th SDC high-to-low transition.

Further information regarding serial control and timing is

shown in

Figure 6., Table 4. and Table 5.

For a minimum interconnect serial environment, the channel

address state can be generated in at least two ways, using an

address counter, or using an address serial to parallel converter.

WR can then be used as the counter clock or shift register load

signal as well as the A/D converter start convert signal on the ris-

ing edge. (Note that the falling edge loads the address present at

the address port.)

SDC

SDO

Figure 6. Serial Data Mode Timing

DB11 (MSB)

DB10

t21

t22

SDC should be in a high state during the STS high period. SDC can make the first high to low transition after t21.

t20

STS

See Table 4

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