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AW9203 Fiches technique(PDF) 4 Page - Shanghai awinic technology co.,ltd |
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AW9203 Fiches technique(HTML) 4 Page - Shanghai awinic technology co.,ltd |
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4 / 30 page ![]() AW9203 June 2018 V1.2 www.awinic.com.cn 4 Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD 1 PIN CONFIGURATION AND TOP MARK Top View 9203-AW9203CSR XXXX-Production Tracing Code Top View SDA AD PDN INT REXT GND S1 S2 S3 CINT GND SCL VBAT 1 2 3 4 A B C D 2 PIN DEFINITION No. NAME DESCRIPTION A1 GND Ground A2 A3 SCL Clock input of I2C Interface A4 VBAT Power supply (3.0V to 4.5V) B1 B2 SDA Data I/O of I2C Interface B3 AD I2C Address Select B4 PDN Power-down input , low active, internal 1M Ω pull-down resistor C1 C2 INTN Open-drain Interrupt output, low active. Typically connected to VIO via a 4.7k Ω resistor C3 REXT External resistor for adjusting sensitivity (typical is 10k Ω) C4 GND Ground D1 S1 Capacitive Touch Input S1 D2 S2 Capacitive Touch Input S2 D3 S3 Capacitive Touch Input S3 D4 CINT External reference capacitor(typical is 4.7nF) |
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