GPLB37A5 datasheet(8/20 Pages) GENERALPLUS

8 / 20 page

GPLB37A5

Proprietary & Confidential

Dec. 23, 2015

Version: 1.0

The following figure is the GPLB37A5 state diagram:

HALT

OPERATING

STANDBY

Write $07h to

CPU_Clk_Ctrl register,

32768 oscillator OFF

Wake-up or user reset

GPLB37A5 State Diagram

6.7. Speech and Melody

For

speech

synthesis,

GPLB37A5

provides

several

timer

interrupts for a precise sampling frequency.

The sound data can

be stored into ROM and be played back.

Several algorithms are

recommended for high fidelity and good compression of sound

such as PCM and ADPCM.

For melody synthesis, the GPLB37A5 provides a dual tone mode.

Once in the dual tone mode, users only need to program the tone

frequency for each channel by writing to the timer/counter TM0

and TM1, and set the envelope of each channel.

The hardware

will toggle the tone wave automatically.

6.8. LCD Controller/Driver

The GPLB37A5 contains a 2048-dot LCD controller/driver.

Programmers are able to define the LCD configuration by setting

up the LCD Control Register.

Once the LCD configuration is

completed, the desired pattern can be displayed by filling the LCD

buffer with proper data.

The LCD driver can also operate during

sleep by keeping 32768 oscillator running.

The LCD driver in

GPLB37A5 supports 1/16-1/32 duty and 1/5-1/6 bias.

6.9. LCD Voltage Generation

The GPLB37A5 offers a voltage regulator and a charge-pumping

circuit.

The voltage regulator provides a reference voltage (V2)

for the charge-pumping circuit to generate VLCD.

Users can get

the desired VLCD by changing the output reference voltage (writing

to register) of the voltage regulator.

Enabling the voltage

regulator and charge-pumping circuit gets a stable VLCD that will

not be affected by VDD.

The VLCD is adjustable from 2.95V to

6.85V at 1/6 bias and from 2.45V to 5.75V at 1/5 bias.

6.10. Audio Output

Internally, the GPLB37A5 supports two audio output modes: PWM

or DAC.

The GPLB37A5 has a pair of PWM drivers, supporting

two sound channels.

Each channel is able to play speech or tone

individually.

The PWM drivers can directly drive speaker or

buzzer without buffer or amplification circuit.

In DAC mode, GPLB37A5 supports 2-channel DAC current output

with 8-bit resolution.

The DAC current signal of each channel

outputs through pin AUDA and AUDB respectively.

6.11. Serial SRAM Interface

The Serial SRAM interface is able to expand the data storage

SRAM.

The Control Registers are $30-$36.

Note that the pins

of SDA and SCK are shared with PC [1:0] and therefore, users

should set PC [1:0] as Serial SRAM interface.

SDA

SCK

change of data

allowed

data line

stable;

data valid

START condition (S)

SDA

SCK

STOP condition (P)

6.11.1. Read/Write timing

R/WA23

D6 D5 D4 D3 D2 D1 D0

SDA

SCK

stop

start

6.11.2. Continuous READ/WRITE timing

R/WA23

D0 D7

SDA

SCK

addr

stop

start

addr+1

addr+n

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