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AR8327-AL1A-R Fiches technique(PDF) 343 Page - List of Unclassifed Manufacturers

No de pièce AR8327-AL1A-R
Description  Seven-port Gigabit Ethernet Switch
PDF  394 Pages
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Fabricant  ETC2 [List of Unclassifed Manufacturers]
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AR8327-AL1A-R Fiches technique(HTML) 343 Page - List of Unclassifed Manufacturers

Back Button AR8327-AL1A-R Datasheet HTML 339Page - List of Unclassifed Manufacturers AR8327-AL1A-R Datasheet HTML 340Page - List of Unclassifed Manufacturers AR8327-AL1A-R Datasheet HTML 341Page - List of Unclassifed Manufacturers AR8327-AL1A-R Datasheet HTML 342Page - List of Unclassifed Manufacturers AR8327-AL1A-R Datasheet HTML 343Page - List of Unclassifed Manufacturers AR8327-AL1A-R Datasheet HTML 344Page - List of Unclassifed Manufacturers AR8327-AL1A-R Datasheet HTML 345Page - List of Unclassifed Manufacturers AR8327-AL1A-R Datasheet HTML 346Page - List of Unclassifed Manufacturers AR8327-AL1A-R Datasheet HTML 347Page - List of Unclassifed Manufacturers Next Button
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Atheros Communications, Inc.
AR8327/AR8327N Seven-port Gigabit Ethernet
Switch
•
343
3.10 PHY Control Registers
Table 3-363, “PHY Control Register Summary,” on page 343 summarizes the PHY Control register
Table 3-364, “PHY Control Register Summary — MMD3,” on page 344 summarizes the PHY Control
Table 3-363.
PHY Control Register Summary
Offset (Hex)
Description
Page
0
Control Register
1
Status Register
2PHY Identifier
3
PHY Identifier 2
4
Auto-negotiation Advertisement Register
5
Link Partner Ability Register
6
Auto-negotiation Expansion Register
7
Next Page Transmit Register
8
Link Partner Next Page Register
9
1000Base-T Control Register
A
1000Base-T Status Register
B
Reserved
C
Reserved
D
Reserved
E
Reserved
F
Extended Status Register
10
PHY-specific Control Register
11
PHY-specific Status Register
12
Interrupt Enable Register
13
Interrupt Status Register
14
Extended PHY-specific Register
15
Receive Error Counter Register
16
Virtual Cable Tester Control Register
17
Reserved
18
Reserved
19
Reserved
1A
Reserved
1B
Reserved
1C
Virtual Cable Tester Status Register
1D
Debug port 1 (Address Offset)
1E
Debug port 2 (Data Port)
1F
Reserved



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