AR8327-AL1A-R datasheet(3/394 Pages) ETC2

3 / 394 page

Atheros Communications, Inc.

AR8327/AR8327N Seven-port Gigabit Ethernet Switch

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3

COMPANY CONFIDENTIAL

June 2011

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Table of Contents

General Description ........................................ 1

AR8327/AR8327N Features .......................... 1

AR8327 System Block Diagram .................... 2

Table of Contents ............................................ 3

Revision History ........................................... 11

1 Pin Descriptions .......................... 13

2 Functional Description ............... 23

2.1 Applications ............................................ 23

2.1.1 AP Router Application .............. 23

2.2 Atheros Header ...................................... 24

2.2.1 Transmit ....................................... 25

2.3 Receive ..................................................... 25

2.4 Header for Read/Write Register. ........ 26

2.5 Media Access Controllers (MAC) ........ 26

2.6 Port Status Configuration ..................... 26

2.6.1 Full-Duplex Flow Control ......... 26

2.6.2 Half-Duplex Flow Control ........ 26

2.6.3 Inter-Packet Gap (IPG) ............... 27

2.6.4 Illegal Frames .............................. 27

2.7 ACL .......................................................... 27

2.7.1 ACL Rule ..................................... 27

2.7.2 Action Definition ........................ 28

2.7.3 MAC Pattern ............................... 29

2.7.4 IPv4 Pattern ................................. 30

2.7.5 IPv6 Pattern ................................. 32

2.7.6 Window Pattern .......................... 34

2.7.7 Enhanced MAC Pattern ............. 35

2.7.8 Enhanced MAC Pattern ............. 35

2.8 Register Access ....................................... 36

2.9 LED Control ............................................ 37

2.10 VLANs .................................................... 38

2.10.1 Port-Based VLAN ....................... 38

2.10.2 802.1Q VLANs ............................ 38

2.10.3 VLAN Security ............................ 38

2.10.4 Port Isolation ............................... 39

2.10.5 Leaky VLAN ............................... 39

2.10.6 VLAN Translation ...................... 39

2.10.7 VLAN Translation Table ........... 39

2.10.8 Egress Mode ................................ 40

2.10.9 VLAN Table ................................. 41

2.11 Security and Port Mapping ................. 41

2.12 MIB/Statistics Counters ...................... 43

2.13 Quality of Service (QoS) ...................... 45

2.14 Mirroring ................................................ 45

2.15 Rate Limiting ......................................... 46

2.16 Broadcast Suppression ......................... 46

2.17 IGMP/MLD Snooping ......................... 46

2.17.1 IEEE 802.3 Reserved Group

Addresses Filtering Control ...... 46

2.17.2 802.1X ........................................... 46

2.17.3 Forwarding Unknown ............... 47

2.17.4 MAC Limit .................................. 47

2.18 Spanning Tree ....................................... 47

2.18.1 EEPROM Programming Format 47

2.18.2 Basic Switch Operation .............. 47

2.18.3 Lookup Engine ............................ 47

2.18.4 Automatic Address Learning ... 48

2.18.5 Automatic Address Aging ........ 48

2.18.6 Broadcast/Multicast Storm Control

2.18.7 ARL Table .................................... 48

2.19 HNAT ..................................................... 50

2.19.1 Basic NAT Table ......................... 50

2.19.2 NAPT Entry ................................. 51

2.19.3 Router MAC Address ................ 52

2.19.4 ARP ENTRY ................................ 53

2.20 IEEE 802.3az and Energy Efficient

Ethernet 53

2.20.1 IEEE 802.3az LPI Mode .............. 54

2.21 Memory Map ......................................... 55

3 Register Descriptions ..................57

3.1 Register Address Space (Address Range

0x0000 ~ 0x00FC) 57

3.2 Global Register Summary (Address Range

0x0000 ~ 0x00B4) 58

3.2.1 MASK_CTRL ............................... 59

3.2.2 PORT0 PAD MODE CTRL ........ 59

3.2.3 PORT5 PAD MODE CTRL ........ 60

3.2.4 PORT6 PAD MODE CTRL ........ 61

3.2.5 PWS_REG .................................... 63

3.2.6 GLOBAL_INT0 ........................... 64

3.2.7 GLOBAL_INT1 ........................... 65

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