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SCD1284 Fiches technique(PDF) 27 Page - Intel Corporation |
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SCD1284 Fiches technique(HTML) 27 Page - Intel Corporation |
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27 / 176 page ![]() IEEE 1284-Compatible Parallel Interface Controller — CD1284 Datasheet 27 4.2 Register Usage Table 8 through Table 13 present register tunctionality. SPR 26 8-Bit Binary Value 153 SSR 2F 0 0 0 0 A1284 nInit HstBsy HstClk 154 ZDR 2C 0 0 0 0 A1284 nInit HstBsy HstClk 154 Table 7. Channel Registers — Parallel Port (Selected by Channel 0 in CAR) (Sheet 2 of 2) Name Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page Table 8. Global Registers Name Reset Parallel Init Parallel Tx Parallel Rx Serial Init Serial Tx Serial Rx GPIO Pin Control CAR √√ √ √ √√ √ GFRCR √ GPDIR √ GPIO √ MICR √√ √ MIR √√ PIR √√ PPR √ RICR √√ √ RIR SVRR √ TICR √√ √ TIR √ Table 9. Virtual Registers Name Reset Parallel Init Parallel Tx Parallel Rx Serial Init Serial Tx Serial Rx MISR √√ MIVR √√ PIVR √ √ RDSR (data) √ RDSR (status ) √ RIVR √ TDR √ TIVR √ |
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