ISL6566 datasheet(21/30 Pages) RENESAS

21 / 30 page

ISL6566

FN9178 Rev 4.00

Page 21 of 30

Mar 9, 2006

UPPER MOSFET POWER CALCULATION

In addition to rDS(ON) losses, a large portion of the upper-

MOSFET losses are due to currents conducted across the

input voltage (VIN) during switching. Since a substantially

higher portion of the upper-MOSFET losses are dependent

on switching frequency, the power calculation is more

complex. Upper MOSFET losses can be divided into

separate components involving the upper-MOSFET

switching times, the lower-MOSFET body-diode reverse-

recovery charge, Qrr, and the upper MOSFET rDS(ON)

conduction loss.

When the upper MOSFET turns off, the lower MOSFET does

not conduct any portion of the inductor current until the

voltage at the phase node falls below ground. Once the

lower MOSFET begins conducting, the current in the upper

MOSFET falls to zero as the current in the lower MOSFET

ramps up to assume the full inductor current. In Equation 17,

the required time for this commutation is t1 and the

approximated associated power loss is PUP,1.

At turn on, the upper MOSFET begins to conduct and this

transition occurs over a time t2. In Equation 18, the

approximate power loss is PUP,2.

A third component involves the lower MOSFET reverse-

recovery charge, Qrr. Since the inductor current has fully

commutated to the upper MOSFET before the lower-

MOSFET body diode can recover all of Qrr, it is conducted

through the upper MOSFET across VIN. The power

dissipated as a result is PUP,3.

Finally, the resistive part of the upper MOSFET is given in

Equation 20 as PUP,4.

The total power dissipated by the upper MOSFET at full load

can now be approximated as the summation of the results

from Equations 17, 18, 19 and 20. Since the power

equations depend on MOSFET parameters, choosing the

correct MOSFETs can be an iterative process involving

repetitive solutions to the loss equations for different

MOSFETs and different switching frequencies.

Package Power Dissipation

When choosing MOSFETs it is important to consider the

amount of power being dissipated in the integrated drivers

located in the controller. Since there are a total of three

drivers in the controller package, the total power dissipated

by all three drivers must be less than the maximum

allowable power dissipation for the QFN package.

Calculating the power dissipation in the drivers for a desired

application is critical to ensure safe operation. Exceeding the

maximum allowable power dissipation level will push the IC

beyond the maximum recommended operating junction

temperature of 125°C. The maximum allowable IC power

dissipation for the 6x6 QFN package is approximately 4W at

room temperature. See Layout Considerations paragraph for

thermal transfer improvement suggestions.

When designing the ISL6566 into an application, it is

recommended that the following calculation is used to

ensure safe operation at the desired frequency for the

selected MOSFETs. The total gate drive power losses,

PQg_TOT, due to the gate charge of MOSFETs and the

integrated driver’s internal circuitry and their corresponding

average driver current can be estimated with Equations 21

and 22, respectively.

In Equations 21 and 22, PQg_Q1 is the total upper gate drive

power loss and PQg_Q2 is the total lower gate drive power

loss; the gate charge (QG1 and QG2) is defined at the

particular gate to source drive voltage PVCC in the

corresponding MOSFET data sheet; IQ is the driver total

quiescent current with no load at both drive outputs; NQ1

and NQ2 are the number of upper and lower MOSFETs per

phase, respectively; NPHASE is the number of active

phases. The IQ*VCC product is the quiescent power of the

controller without capacitive load and is typically 75mW at

300kHz.

PUP 1, VIN

------

IPP

---------



 t1

----









(EQ. 17)

PUP 2

VIN

------

IPP

---------

–



 t2

----









(EQ. 18)

PUP 2

VIN

------

IPP

---------

–



 t2

----









PUP 3,

VIN Qrr fS

(EQ. 19)

PUP 4, rDS ON



------





 2

IPP

----------



(EQ. 20)

FIGURE 15. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

PQg_TOT

PQg_Q1 PQg_Q2 IQ VCC



(EQ. 21)

PQg_Q1

--- QG1 PVCC



FSW



NQ1



NPHASE



PQg_Q2

QG2 PVCC



FSW



NQ2 NPHASE



IDR

--- QG1 N



QG2 NQ2





 N

PHASE



FSW IQ



(EQ. 22)

RGI1

RG1

BOOT

RHI1

CDS

CGS

CGD

RLO1

PHASE

PVCC

UGATE

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