ISL6566 datasheet(14/30 Pages) RENESAS

14 / 30 page

ISL6566

FN9178 Rev 4.00

Page 14 of 30

Mar 9, 2006

Voltage Regulation

In order to regulate the output voltage to a specified level,

the ISL6566 uses the integrating compensation network

shown in Figure 6. This compensation network insures that

the steady-state error in the output voltage is limited only to

the error in the reference voltage (output of the DAC) and

offset errors in the OFS current source, remote-sense and

error amplifiers. Intersil specifies the guaranteed tolerance of

the ISL6566 to include the combined tolerances of each of

these elements.

The ISL6566 incorporates an internal differential remote-

sense amplifier in the feedback path. The amplifier removes

the voltage error encountered when measuring the output

voltage relative to the controller ground reference point,

resulting in a more accurate means of sensing output

voltage. Connect the microprocessor sense pins to the non-

inverting input, VSEN, and inverting input, RGND, of the

remote-sense amplifier. The droop voltage, VDROOP, also

feeds into the remote-sense amplifier. The remote-sense

output, VDIFF, is therefore equal to the sum of the output

voltage, VOUT, and the droop voltage. VDIFF is connected to

the inverting input of the error amplifier through an external

resistor.

The output of the error amplifier, VCOMP, is compared to the

sawtooth waveform to generate the PWM signals. The PWM

signals control the timing of the Internal MOSFET drivers

and regulate the converter output so that the voltage at FB is

equal to the voltage at REF. This will regulate the output

voltage to be equal to Equation 4. The internal and external

circuitry that controls voltage regulation is illustrated in

Figure 6.

Load-Line (Droop) Regulation

Some microprocessor manufacturers require a precisely-

controlled output impedance. This dependence of output

voltage on load current is often termed “droop” or “load line”

regulation.

1.2125

1.2250

1.2375

1.2500

1.2625

1.2750

1.2875

101

1.300

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

1.4500

1.4625

1.4750

1.4875

1.5000

1.5125

1.5250

1.5375

1.5500

1.5625

1.5750

1.5875

1.6000

TABLE 4. VRM10 VOLTAGE IDENTIFICATION CODES (Continued)

VID4

VID3

VID2

VID1

VID0

VID12.5

VDAC

FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE

REGULATION WITH OFFSET ADJUSTMENT

IOFS

EXTERNAL CIRCUIT

ISL6566 INTERNAL CIRCUIT

COMP

RFB

VDIFF

VSEN

RGND

VOFS

ERROR AMPLIFIER

DIFFERENTIAL

REMOTE-SENSE

AMPLIFIER

VCOMP

REF

CREF

VID DAC

IREF

ICOMP

VDROOP

VOUT

VREF VOFS

–

VDROOP

–

(EQ. 4)

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