LTC3589-1 datasheet(22/38 Pages) LINER

22 / 38 page

LTC3676/LTC3676-1

3676ff

For more information www.linear.com/LTC3676

Figure 11. Pin-Strapped Power-On Sequence

operaTion

Software Control Mode

Once a power-up sequence is completed, each regulator

may be enabled and disabled individually by the system

as needed for power management requirements by using

the command register bit CNTRL[5]. When CNTRL[5] is

set high the regulators ignore the state of their enable pins

and respond only to I2C command register bit settings.

The software control mode bit is reset in the one second

standby and hard reset timer states so a pin strapped

sequence begins at the next LTC3676 power on.

Keep Alive Operation

Each regulator has a dedicated command register keep

alive bit that, when set, forces a regulator to be enabled

regardless of the enable pins, command register enable

WAKE

VB1

VB2

VB3

VB4

VL2

VL3

VL4

0.4V

450µs

1.2V

1.8V

2.5V

1.2V

1.8V

2.8V

3676 F11

450µs

bits, or the operating state of the LTC3676. A hard reset

or fault shutdown resets the keep alive bits.

POWER OFF SEQUENCING

Sequence down command registers SQD1 and SQD2

are used to set the time, relative to WAKE falling, that a

regulator is disabled either by lowering PWR_ON, or a

fault induced shutdown. Table 10 shows register settings

for SQD1 and SQD2.

Table 10.Sequence Down Control Command Register Settings

COMMAND

VALUE SETTING

SQD1[1:0]

00*

Disable Buck1 at Falling WAKE

Disable Buck1 at Falling WAKE + 100ms

Disable Buck1 at Falling WAKE + 200ms

Disable Buck1 at Falling WAKE + 300ms

SQD1[3:2]

00*

Disable Buck2 at Falling WAKE

Disable Buck2 at Falling WAKE + 100ms

Disable Buck2 at Falling WAKE + 200ms

Disable Buck2 at Falling WAKE + 300ms

SQD1[5:4]

00*

Disable Buck3 at Falling WAKE

Disable Buck3 at Falling WAKE + 100ms

Disable Buck3 at Falling WAKE + 200ms

Disable Buck3 at Falling WAKE + 300ms

SQD1[7:6]

00*

Disable Buck4 at Falling WAKE

Disable Buck4 at Falling WAKE + 100ms

Disable Buck4 at Falling WAKE + 200ms

Disable Buck4 at Falling WAKE + 300ms

SQD2[1:0]

00*

Disable LDO2 at Falling WAKE

Disable LDO2 at Falling WAKE + 100ms

Disable LDO2 at Falling WAKE + 200ms

Disable LDO2 at Falling WAKE + 300ms

SQD2[3:2]

00*

Disable LDO3 at Falling WAKE

Disable LDO3 at Falling WAKE + 100ms

Disable LDO3 at Falling WAKE + 200ms

Disable LDO3 at Falling WAKE + 300ms

SQD2[5:4]

00*

Disable LDO4 at Falling WAKE

Disable LDO4 at Falling WAKE + 100ms

Disable LDO4 at Falling WAKE + 200ms

Disable LDO3 at Falling WAKE + 300ms

*denotes default power-on value.

Figure 12 shows an example of a shutdown sequence. In

this example, the bits in command registers SQD1 and

SQD2 are set so that LDO2, LDO3, and LDO4 shut off at

the same time as WAKE. Buck2 and Buck4 shut off 100ms

after WAKE. Buck3 shuts off 200ms after wake and Buck1

shuts off 300ms after WAKE.

Figure 10. Pin-Strapped Power-On Sequence Application

LTC3676

VIN

PWR_ON

3676 F10

VB1 = 1.2V

VB2 = 1.8V

VB3 = 2.5V

VB4 = 1.2V

VL2 = 1.2V

VL3 = 1.8V

VL4 = 2.8V

WAKE

SW1

SW2

SW3

SW4

LDO2

LDO3

LDO4

EN_B1

EN_B2

EN_B3

EN_B4

EN_L2

EN_L3

EN_L4

PWR_ON

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