LTC3589-1 datasheet(11/38 Pages) LINER

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LTC3676/LTC3676-1

3676ff

For more information www.linear.com/LTC3676

pin FuncTions

FB_L2 (Pin 1/Pin 2): Feedback Input for LDO2. Set full-

scale output voltage using a resistor divider connected

from LDO2 to this pin to ground.

VIN_L2 (Pin 2/Pin 3): Power Input for LDO2. This pin

should be bypassed to ground with a 1μF or greater

ceramic capacitor.Voltage on VIN_L2 should not exceed

voltage on VIN pin.

LDO2 (Pin 3/Pin 4): Output Voltage of LDO2. Nominal

output voltage is set with a resistor feedback divider that

servos to a fixed 725mV reference. This pin must be by-

passed to ground with a 1µF or greater ceramic capacitor.

LDO3 (Pin 4/Pin 5): Output Voltage of LDO3. Nominal

output voltage is a fixed 1.8V. This pin must be bypassed

to ground with a 1µF or greater ceramic capacitor.

VIN_L3 (Pin 5/Pin 6): Power Input for LDO3. This pin

should be bypassed to ground with a 1µF or greater

ceramic capacitor.Voltage on VIN_L3 should not exceed

voltage on VIN pin.

LDO4 (Pin 6/Pin 7): Output Voltage of LDO4. Nominal

output voltage is set with a resistor feedback divider that

servos to a fixed 725mV reference. This pin must be by-

passed to ground with a 1µF or greater ceramic capacitor.

VIN_L4 (Pin 7/Pin 8): Power Input for LDO4. This pin

should be bypassed to ground with a 1μF or greater

ceramic capacitor.Voltage on VIN_L4 should not exceed

voltage on VIN pin.

FB_L4 (Pin 8/Pin 9): Feedback Input for LTC3676 LDO4.

Set full-scale output voltage using a resistor divider con-

nected from LDO4 to this pin to ground.

VDDQIN (Pin 8/Pin 9): VDD Sense Input for LTC3676-1.

Tie DDR memory VDD supply to this pin.

EN_L4 (Pin 9/Pin 10): Enable LDO4 Input for LTC3676.

Active high enables LDO4. A weak pull-down pulls EN_L4

low when left floating.

VTTR (Pin 9/Pin 10): DDR VREF Output Pin for LTC3676-1.

Buffered reference equal to one-half VDDQIN voltage on

Pin 8.

EN_L3 (Pin 10/Pin 11): Enable LDO3 Input. Active high

enables LDO3. A weak pull-down pulls EN_L3 low when

left floating.

SW4 (Pin 11/Pin 14): Switch Pin for Step-Down Switch-

ing Regulator 4. Connect one side of step-down switching

regulator 4 inductor to this pin.

DVDD (Pin 12/Pin 15): Supply Voltage for I2C Serial Port.

This pin sets the logic reference level of SCL and SDA I2C

pins. DVDD resets I2C registers to power-on state when

driven to <1V. SCL and SDA logic levels are scaled to

DVDD. Connect a 0.1µF decoupling capacitor from this

pin to ground.

SDA (Pin 13/Pin 16): Data Pin for the I2C Serial Port. The

I2C logic levels are scaled with respect to DVDD.

SCL (Pin 14/Pin 17): Clock Pin for the I2C Serial Port. The

I2C logic levels are scaled with respect to DVDD.

PVIN4(Pin15/Pin18):PowerInputforStep-DownSwitch-

ing Regulator 4. Tie this pin to VIN supply. This pin should

be bypassed to ground with a 10μF or greater ceramic

capacitor.

PVIN3(Pin16/Pin19):PowerInputforStep-DownSwitch-

ing Regulator 3. Tie this pin to the VIN supply. This pin

should be bypassed to ground with a 10μF or greater

ceramic capacitor.

EN_B4 (Pin 17/Pin 20): Enable Step-Down Switching

Regulator 4.Activehighinputenablesstep-downswitching

regulator 4. A weak pull-down pulls EN_B4 low when left

floating.

EN_B3 (Pin 18//Pin 21): Enable Step-Down Switching

Regulator 3.Activehighinputenablesstep-downswitching

regulator 3. A weak pull-down pulls EN_B3 low when left

floating.

VSTB (Pin 19/Pin 22): Voltage Standby. When VSTB is

low, the DAC registers are selected by command register

bit DVBxA[5]. When VSTB is high, the DAC registers are

forced to DVBxB registers. Tie VSTB to ground if unused.

SW3 (Pin 20/Pin 23): Switch Pin for Step-Down Switch-

ing Regulator 3. Connect one side of step-down switching

regulator 3 inductor to this pin.

PWR_ON(Pin21/Pin26):ExternalPowerOn.Handshaking

pin to acknowledge successful power-on sequence.

PWR_ON must be driven high within five seconds of

WAKE going high to keep power on. PWR_ON can be

(QFN/LQFP)

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